Memory systems comprising pluralities of memory elements or Basic Storage Modules (BSMs) as illustrated in FIG. 1 are well known in the State of the Art. Further, it is known that these memory elements may include a plurality of rows of memory chips such as, for example, 8 rows. Each chip may include a plurality of 8 or 9 bit wide arrays or islands. Each island comprises 32K bit arrays. In the prior art when one accesses a given chip group in a row doing either a fetch or a store command the entire BSM or memory element is held busy for whatever number of cycles until the fetch and the store is complete. U.S. Pat. No. 4,924,375 describes page interleaved memory access. This is a technique for accessing pages by having banks of memory elements activated separately. U.S. Pat. No. 4,954,987 discloses an interleaved sensing system for FIFO and burst mode memories. U.S. Pat. Nos. 3,863,232 and 3,449,723 show interleaving memory systems and U.S. Pat. Nos. 4,117,546, 4,558,436 and 4,816,916 show interlacing of chips. U.S. Pat. No. 4,816,916 discloses a CCD area image sensor operable in both line sequential and interlace scannings and a method for operating the same. The prior art requires a multitude of machine cycles to store or retrieve data from a given memory element.
An object of the present invention is to provide a high data rate to and from memory systems and the servicing of a high number of requests simultaneously.